VHDL text IO manipulation

VHDL text IO manipulation is significantly needed while we are designing self-checking test bench. Text IO manipulation is very easy in Verilog. I guess it so in VHDL, but it is a little different.

The very basic method is using assertion. Investigate the syntax below!

    assert (counter_out=1) report "this is not the expected signal " severity error;

the second method is using textio library

use std.textio.all;

entity simple_textio is
end;

architecture simple_behavior of simple_textio is
begin
process
  variable i  : integer:= 42;
  variable lll: line;
begin
  write    (lll   , i  );
  writeline(output, lll);
  wait;
end process;

end simple_behavior;

now, how to display variable/signal value to screen?

Ok, I will complete my explanation later. Just try to understand my testbench code below. If you have any question, you can put comment or send me email. Thank you

-- ======================================================================= --
--  Name        : counter_tb.vhd                                           --
--  Author      : Norma Hermawan                                           --
--  Version     : alpha                                                    --
--  Copyright   : This program is used as lab assignment. Do not copy !    --
--  Description : Testbench of counter_tb module                           --
-- ======================================================================= --

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.txt_util.all;

entity counter_tb is
--   generic(n: INTEGER := 2);
end counter_tb;

architecture self_sequential of counter_tb is
  constant n           : integer := 2;
  signal   clk_in      : std_logic;
  signal   reset_in    : std_logic;
  signal   enable_in   : std_logic;
  signal   counter_out : std_logic_vector(n-1 downto 0);
begin
   
 
  DUT: entity work.n_bit_counter
  generic map(n)
  port map(clk_in, reset_in, enable_in, counter_out);
 
  clock_gen : process
  begin
    clk_in      <= '0';
    wait for 5 ns;
    clk_in      <= '1';
    wait for 5 ns;
  end process clock_gen;
 
  sequence: process
  begin
    reset_in    <= '1';
    enable_in   <= '1';
    wait for 20 ns;
   
    reset_in    <= '0';
    wait for 50 ns;

    enable_in   <= '0';
    wait;
  end process sequence;
 
  test_vector : process
    variable counter_cmp : integer := 0;
  begin
    wait on clk_in;
    if (clk_in'event and clk_in = '1') then
       if (enable_in = '1') and (reset_in = '0') then
          if counter_cmp = 3 then
            counter_cmp := 0;
          else 
            counter_cmp := counter_cmp + 1;
          end if;
         
          wait for 1 ns; -- component delay
          if (counter_cmp = counter_out) then
             assert false report "PASS : Actual : " & str(counter_out) & " Expected : " & str(counter_cmp) severity note;
          else  
             assert false report "FAIL : Actual : " & str(counter_out) & " Expected : " & str(counter_cmp) severity note;
          end if;
       end if;
    end if;
  end process test_vector;
 
 
 
end architecture self_sequential;

and I am successfull to make this in modelsim

# Refreshing ./work.n_bit_counter(behv)
# Loading work.n_bit_counter(behv)
# PASS : Actual : 01 Expected : 1
# PASS : Actual : 10 Expected : 2
# PASS : Actual : 11 Expected : 3
# PASS : Actual : 00 Expected : 0
# PASS : Actual : 01 Expected : 1

You just need to make a little modification in modelsim.ini

; AssertionFormatNote      = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
AssertionFormatNote      = "%R\n"

The o ther method is creating custon printf() function utilizing textio library.

http://www.stefanvhdl.com/