VHDL port Array

the solution is to declare
Data Types 33
TLFeBOOK
user-defined data types in a PACKAGE, which will then be visible to the whole design
(thus including the ENTITY). An example is shown below.

------- Package: --------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------
PACKAGE my_data_types IS
TYPE vector_array IS ARRAY (NATURAL RANGE <>) OF
STD_LOGIC_VECTOR(7 DOWNTO 0);
END my_data_types;
--------------------------------------------

Source: Circuit Design with VHDL, Volnei A. Pedroni
MIT Press